Not Applicable
The present invention pertains generally to apparatus for supporting semiconductor wafers during thermal processing and particularly to apparatus for supporting silicon wafers during high temperature processing such that gravitational stresses are mitigated.
Modern microelectronic devices or integrated circuits (ICs) are fabricated using processes in which hundreds of individual ICs or dies are produced simultaneously on a single silicon wafer. The production of ICs generally requires several dozen thermal and deposition processes, all of which are performed on these monolithic single-crystal wafers. These processes are performed either in single-wafer tools or in large batch furnaces containing up to a few hundred wafers. After processing, the wafers are cut apart to produce individual IC dies.
The historical trends of reduced IC costs and increased productivity in microelectronics manufacturing have been obtained in part by employing progressively larger silicon wafers. Increasing the silicon wafer size allows more IC dies to be produced from each silicon wafer. This reduces unit IC costs by reducing handling costs and by increasing the areal throughputs of both batch and single-wafer tools. The trend of increasing silicon wafer size is also driven in part by the continuously increasing size of IC dies. As die sizes increase, the silicon wafer size must also increase to permit the same number of dies on each wafer. Current production wafers range in diameter up to 200 mm, but the introduction of 300 mm wafers is now under way.
As silicon wafers are heated and cooled during thermal and deposition processes, temperature variations arise across the wafer face. These temperature variations give rise to thermal stress in the wafer. If the thermal stress exceeds the yield strength of the wafer, slip lines or other microstructural defects will be produced in the wafer crystal. Such defects lead to failure of IC devices and so must be strictly avoided. Consequently, the importance of controlling thermal stress has been widely recognized. The heating and cooling rates and the push and pull rates at which silicon wafers are inserted into or withdrawn from batch furnaces have both been reduced for larger wafer sizes in order to reduce temperature variations across the wafers. On the other hand, it is desirable to increase heating and cooling rates in order to increase wafer throughput. Recently, new batch furnace designs have been developed in which the wafer spacing is increased to reduce temperature variations and so permit more rapid heating and cooling.
Thermal stress is just one of several size-dependent sources of stress in silicon wafers. As wafer sizes increase, gravitational stress also increases. Like thermal stress, gravitational stress will lead to crystal defects if their values exceed the yield strength of the wafer. These stresses arise from supporting the weight of the wafer on a limited number of points and originate both from the local effects of the support and, more importantly, from bending of the wafer due to its weight in unsupported regions. In the past, wafer diameters were small enough and wafer thicknesses were sufficiently large such that gravitational stresses were quite small. As such, gravitational stresses have not been a serious concern, and a wide variety of support methods have been used successfully for wafer sizes up to 200 mm.
Silicon wafer thicknesses have historically increased at rates much lower than those of wafer diameters. Nominal wafer thicknesses are 625, 725 and 775 xcexcm at wafer diameters of 150, 200 and 300 mm. Since gravitational stresses generally scale as the square of the wafer diameter and inversely as the wafer thickness, gravitational stresses will increase even if the wafer thickness grew in proportion to the wafer size. As a result, gravitational stresses have increased dramatically with increasing wafer size for any fixed support geometry. The increasing importance of gravitational stresses and the necessity for reducing or eliminating gravitational stresses by providing proper support for wafers during thermal processing has been recognized as described in U.S. Pat. Nos. 5,492,229 and 5,605,574, by way of example.
FIG. 1 illustrates the influence of wafer size on gravitational stress for the wafer thickness variation shown by the dotted line in FIG. 2. Here the computed maximum shear stress appearing anywhere on the wafer is shown for several common support geometries (B, C, and D). The common geometries are: (B) a single ring located at about 70% of the wafer radius; (C) a single ring located at the wafer edge; and (D) a three-point support having support locations at the wafer edge and at angular positions of 0, 90, and 180 degrees. The last of these is a very common support geometry for batch furnaces because it permits insertion and withdrawal of the wafers from the front of the multi-wafer support structure referred to as a boat.
FIG. 1 shows that gravitational stress increases rapidly with increasing wafer size. Between 200 and 300 mm wafer diameters, the maximum gravitational stress roughly doubles for all support geometries. Further, the method of support plays an important role in determining these stresses. The maximum shear stress on a wafer for three point support is about a factor of ten above that for an edge ring and nearly a factor of forty above that for a ring placed well in from the wafer edge (70% of the wafer diameter).
Gravitational stresses do not vary with temperature they depend only on the wafer diameter, wafer thickness and the support geometry. In contrast, the strength of silicon falls rapidly as the temperature is increased. As a result, the fixed gravitational stress becomes a larger fraction of the decreasing yield strength as the silicon wafer temperature is increased. With increasing temperatures, the yield strength of the silicon wafer decreases to the point at which it becomes equal to the gravitational stress. At this point, the strength of the silicon has dropped to a level where the silicon wafer is failing under the stress of its own weight. It will then deform plastically, and defects will be produced in the crystal structure of the silicon wafer. This behavior has an important practical consequence in limiting both the maximum possible processing temperature as well as the allowable ramp rate (the rate at which the furnace and the silicon wafer temperatures increase or decrease).
Allowable ramp rates and maximum operating temperatures of batch furnaces are limited by the combined effects of thermal and gravitational stresses. As described hereinabove, thermal stress arises from the radial temperature gradients associated with heating and cooling of wafers. Faster ramp rates produce larger temperature differences and, hence, larger thermal stresses. Gravitational stress is associated with bending of the wafer under its own weight. With increasing wafer diameter, thermal stress remains invariant (for a given radial temperature difference) while gravitational stress increases as the square of the wafer diameter. Thus, as the wafer size increases the reduction of gravitational stress becomes of increasing importance in allowing higher maximum operating temperatures and increased furnace ramp rates.
FIG. 2 shows computed maximum allowable processing temperatures as a function of wafer size for the support geometries previously considered in FIG. 1. Note that support geometry has a strong influence on the maximum temperature. For a 200 mm wafer, the maximum temperature that can be sustained varies by almost 400xc2x0 C. between the three-point and ring support geometries (B, C, and D). Further, for a 300 mm wafer the maximum processing temperature for the three point geometry is just above 900xc2x0 C. This is well below the desired maximum of about 1200xc2x0 C. needed to accommodate the full range of thermal and deposition processes. Similarly, the computed maximum for a 300 mm wafer supported by a full edge ring (FIG. 2, curve C) is only about 1150xc2x0 C. Thus even this better support geometry will likely not be sufficient for all processes of practical interest. Although many of the maximum temperatures shown in FIG. 2 are above those of practical interest, these results include only gravitational stress. Other sources, such as thermal and film stresses, will also contribute to the total stress and thus will reduce the maximum allowable temperature.
Ring supports tend to minimize gravitational stress relative to point supports by reducing stresses near the support locations. For most placements of a single ring, the maximum stress occurs not at the support location, but instead near the center or edge of the wafer. It is known in the art that gravitational stress is minimized for a single ring support if the ring diameter is about 70% of the wafer diameter, regardless of the wafer size. This is one of the geometries considered in the results shown in FIGS. 1 and 2. For a 300 mm wafer, this support geometry gives a maximum allowable processing temperature of about 1300xc2x0 C. Although this is above most temperatures of practical importance, combined thermal and gravitational stresses would likely yield an actual maximum temperature that is below the desired values for some processes. Moreover, the single ring support is undesirable for batch wafer processing applications because it obstructs front end loading of a batch furnace. Therefore, there is a need for further reduction of gravitational stress coupled with a geometry that will not obstruct efficient loading and unloading of a batch furnace or single wafer processor.
The present invention provides a novel support apparatus for semiconductor wafers, and particularly silicon wafers, that offers a significant reduction in the magnitude of gravitational stress for all wafer sizes during thermal processing. As silicon wafer diameters increase beyond 200 mm, reductions in gravitational stress will become increasingly important with respect to the continued use of high-temperature thermal and deposition processes in microelectronics manufacturing. Because reducing gravitational stress will permit higher heating and cooling rates in batch furnaces, this apparatus will also help reduce processing times and costs. Finally, the claimed wafer support apparatus can be readily adapted for use in either batch or single-wafer processors.